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    <meta name="description" content="Verilog1. Verilog语言如何用于模拟电路设计的Verilog是一种硬件描述语言（HDL），通常用于模拟和设计数字电路。下面是使用Verilog语言进行电路设计和模拟的一般步骤：  编写Verilog代码：首先，您需要编写Verilog代码来描述您的电路。Verilog代码将包括模块定义、输入和输出端口、内部逻辑以及任何需要的组件实例化。这个代码将描述电路的结构和功能。  设计层次结构">
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            <div class="post-toc animated"><ol class="nav"><li class="nav-item nav-level-2"><a class="nav-link" href="#Verilog"><span class="nav-number">1.</span> <span class="nav-text">Verilog</span></a><ol class="nav-child"><li class="nav-item nav-level-3"><a class="nav-link" href="#1-Verilog%E8%AF%AD%E8%A8%80%E5%A6%82%E4%BD%95%E7%94%A8%E4%BA%8E%E6%A8%A1%E6%8B%9F%E7%94%B5%E8%B7%AF%E8%AE%BE%E8%AE%A1%E7%9A%84"><span class="nav-number">1.1.</span> <span class="nav-text">1. Verilog语言如何用于模拟电路设计的</span></a></li><li class="nav-item nav-level-3"><a class="nav-link" href="#2-%E7%BC%96%E5%86%99Verilog%E4%BB%A3%E7%A0%81"><span class="nav-number">1.2.</span> <span class="nav-text">2. 编写Verilog代码</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#2-1-%E5%BB%BA%E6%A8%A1%E6%96%B9%E5%BC%8F"><span class="nav-number">1.2.1.</span> <span class="nav-text">2-1. 建模方式</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#2-2-%E5%B8%B8%E7%94%A8%E7%9A%84%E8%AF%AD%E6%B3%95"><span class="nav-number">1.2.2.</span> <span class="nav-text">2-2. 常用的语法</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#1-%E5%8F%98%E9%87%8F%E7%B1%BB%E5%9E%8B"><span class="nav-number">1.2.2.1.</span> <span class="nav-text">(1) 变量类型</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#2-%E8%BF%9E%E7%BB%AD%E8%BF%87%E7%A8%8B%E8%B5%8B%E5%80%BC"><span class="nav-number">1.2.2.2.</span> <span class="nav-text">(2) 连续过程赋值</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#3-always%E8%AF%AD%E5%8F%A5"><span class="nav-number">1.2.2.3.</span> <span class="nav-text">(3) always语句</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#4-%E8%BF%87%E7%A8%8B%E8%B5%8B%E5%80%BC"><span class="nav-number">1.2.2.4.</span> <span class="nav-text">(4) 过程赋值</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#5-%E5%87%BD%E6%95%B0"><span class="nav-number">1.2.2.5.</span> <span class="nav-text">(5) 函数</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#6-generate"><span class="nav-number">1.2.2.6.</span> <span class="nav-text">(6) generate</span></a></li></ol></li></ol></li><li class="nav-item nav-level-3"><a class="nav-link" href="#3-Verilog%E5%BC%80%E5%8F%91%E5%B7%A5%E5%85%B7"><span class="nav-number">1.3.</span> <span class="nav-text">3. Verilog开发工具</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#3-1-Verilator"><span class="nav-number">1.3.1.</span> <span class="nav-text">3-1 Verilator</span></a></li></ol></li></ol></li></ol></div>
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    <div class="post-body" itemprop="articleBody"><h2 id="Verilog"><a href="#Verilog" class="headerlink" title="Verilog"></a>Verilog</h2><h3 id="1-Verilog语言如何用于模拟电路设计的"><a href="#1-Verilog语言如何用于模拟电路设计的" class="headerlink" title="1. Verilog语言如何用于模拟电路设计的"></a>1. Verilog语言如何用于模拟电路设计的</h3><p>Verilog是一种硬件描述语言（HDL），通常用于模拟和设计数字电路。下面是使用Verilog语言进行电路设计和模拟的一般步骤：</p>
<ol>
<li><p><strong>编写Verilog代码</strong>：首先，您需要编写Verilog代码来描述您的电路。Verilog代码将包括模块定义、输入和输出端口、内部逻辑以及任何需要的组件实例化。这个代码将描述电路的结构和功能。</p>
</li>
<li><p><strong>设计层次结构</strong>：将电路分解为模块和子模块，以便更容易管理和维护代码。这有助于提高代码的可重用性和可维护性。</p>
</li>
<li><p><strong>模拟器选择</strong>：选择一个Verilog模拟器，如XSIM、ModelSim、VCS等。模拟器将用于运行Verilog代码并模拟电路的行为。</p>
</li>
<li><p><strong>创建测试台</strong>：编写测试台代码，用于提供输入信号并捕获输出信号。测试台代码通常包括测试向量生成、时钟生成以及对电路行为的监视。</p>
</li>
<li><p><strong>编译和仿真</strong>：使用Verilog模拟器编译Verilog代码并运行仿真。仿真将模拟电路的运行，并根据输入信号模拟输出信号。</p>
</li>
<li><p><strong>分析仿真结果</strong>：分析仿真输出以验证电路的正确性。检查输出是否与预期结果一致，以确保电路按照设计规范工作。</p>
</li>
<li><p><strong>优化和修改</strong>：根据仿真结果，对Verilog代码进行优化或修改，以改进电路性能或修复问题。</p>
</li>
<li><p><strong>重复测试</strong>：重复上述步骤，直到满足设计规范和性能要求。</p>
</li>
<li><p><strong>综合和实际实现</strong>：一旦满足了设计规范，可以将Verilog代码综合成门级电路，并使用工具如Xilinx Vivado、Synopsys Design Compiler等将其映射到FPGA或ASIC。</p>
</li>
<li><p><strong>验证硬件</strong>：在实际硬件上验证电路，确保它在实际环境中正常工作。</p>
</li>
</ol>
<p>总之，Verilog语言是一种强大的工具，用于模拟和设计数字电路。通过编写Verilog代码并使用仿真器，您可以有效地验证电路的功能和性能，然后将其实现在硬件中。这个过程通常在数字电路设计中扮演着关键的角色。</p>
<span id="more"></span>

<h3 id="2-编写Verilog代码"><a href="#2-编写Verilog代码" class="headerlink" title="2. 编写Verilog代码"></a>2. 编写Verilog代码</h3><h4 id="2-1-建模方式"><a href="#2-1-建模方式" class="headerlink" title="2-1. 建模方式"></a>2-1. 建模方式</h4><ul>
<li><p>结构化建模</p>
<p>结构化建模主要通过逐层实例化子模块的方式来描述电路的功能。</p>
</li>
<li><p>数据流建模</p>
</li>
</ul>
<p>​		数据流建模主要是通过连续赋值语句 <code>assign</code> 来描述电路的功能</p>
<ul>
<li>行为建模</li>
</ul>
<h4 id="2-2-常用的语法"><a href="#2-2-常用的语法" class="headerlink" title="2-2. 常用的语法"></a>2-2. 常用的语法</h4><h5 id="1-变量类型"><a href="#1-变量类型" class="headerlink" title="(1) 变量类型"></a>(1) 变量类型</h5><p>类型主要用到有： wire、reg、 parameter </p>
<ul>
<li>wire 类型表示<strong>硬件单元之间的物理连线</strong>， 本身并没有记忆的功能。如果没有驱动元件连接到 wire 型变量，缺省值一般为 “Z”。</li>
<li>reg 类型用来表示存储单元，它会保持数据原有的值，直到被改写</li>
<li>parameter 类型用来表示常量，只能被定义一次</li>
</ul>
<h5 id="2-连续过程赋值"><a href="#2-连续过程赋值" class="headerlink" title="(2) 连续过程赋值"></a>(2) 连续过程赋值</h5><p>连续过程赋值使用关键词<code>assign</code> 对 <code>wire</code>类型的变量进行赋值</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">assign LHS_target = RHS_expression  </span><br></pre></td></tr></table></figure>

<ul>
<li>LHS_target 必须是一个标量或者线型向量，而<strong>不能是寄存器类型</strong>。</li>
<li>RHS_expression 的类型没有要求，可以是标量或线型或存器向量，也可以是函数调用。</li>
<li>只要 RHS_expression 表达式的操作数有事件发生（值的变化）时，RHS_expression 就会<strong>立刻重新计算</strong>，同时赋值给 LHS_target。</li>
</ul>
<h5 id="3-always语句"><a href="#3-always语句" class="headerlink" title="(3) always语句"></a>(3) always语句</h5><p>一个模块中可以包含多个 always 语句，这些语句在模块间<strong>并行执行</strong>，与其在模块的前后顺序没有关系。（此处会出现问题，涉及过程赋值）</p>
<p>always 语句块从 0 时刻开始执行其中的行为语句；当执行完最后一条语句后，便再次执行语句块中的第一条语句，如此循环反复。</p>
<h5 id="4-过程赋值"><a href="#4-过程赋值" class="headerlink" title="(4) 过程赋值"></a>(4) 过程赋值</h5><p>过程性赋值是在 initial 或 always 语句块里的赋值，<strong>赋值对象是寄存器、整数、实数等类型</strong>， 过程赋值包括阻塞赋值和非阻塞赋值。</p>
<p><strong>非阻塞(Non_Blocking)赋值方式( 如 b &lt;&#x3D; a; )</strong></p>
<ul>
<li>块结束后才完成赋值操作。</li>
<li>b的值并不是立刻就改变的。</li>
<li>这是一种比较常用的赋值方法。（特别在编写可综合模块时）</li>
</ul>
<p><strong>阻塞(Blocking)赋值方式( 如 b &#x3D; a; )</strong></p>
<ul>
<li>赋值语句执行完后,块才结束。</li>
<li>b的值在赋值语句执行完后立刻就改变的。</li>
<li>可能会产生意想不到的结果。</li>
</ul>
<p><strong>在描述组合逻辑的always 块中用阻塞赋值，则综合成组合逻辑的电路结构。在描述时序逻辑的always 块中用非阻塞赋值，则综合成时序逻辑的电路结构</strong></p>
<h5 id="5-函数"><a href="#5-函数" class="headerlink" title="(5) 函数"></a>(5) 函数</h5><p>在 Verilog 中，可以利用任务（关键字为 task）或函数（关键字为 function），将重复性的行为级设计进行提取，并在多个地方调用，来避免重复代码的多次编写，使代码更加的简洁、易用</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">function [range-1:0]     function_id ;</span><br><span class="line">input_declaration ;</span><br><span class="line"> other_declaration ;</span><br><span class="line">procedural_statement ;</span><br><span class="line">endfunction</span><br></pre></td></tr></table></figure>

<h5 id="6-generate"><a href="#6-generate" class="headerlink" title="(6) generate"></a>(6) generate</h5><p><code>generate</code>关键字用于在编译时生成模块的一部分代码。<code>generate</code>块允许根据条件、参数或其他参数化的方式生成不同的硬件描述。这对于需要根据设计配置或条件生成不同版本的电路非常有用。</p>
<ul>
<li><strong>条件生成</strong>：生成块可以根据条件来包含或排除特定的硬件描述。例如，您可以根据参数来选择是否包含某个模块：</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">verilogCopy codegenerate</span><br><span class="line">if (ENABLE_FEATURE) begin</span><br><span class="line">  // 生成某个模块或逻辑</span><br><span class="line">end</span><br><span class="line">endgenerate</span><br></pre></td></tr></table></figure>

<ul>
<li><strong>循环生成</strong>：<code>generate</code>块可以用于生成重复的硬件元素，例如一组相似的输入通道或处理单元：</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">verilogCopy codegenerate</span><br><span class="line">for (i = 0; i &lt; N; i = i + 1) begin</span><br><span class="line">  // 生成N个相似的硬件元素</span><br><span class="line">end</span><br><span class="line">endgenerate</span><br></pre></td></tr></table></figure>

<ul>
<li><strong>参数化生成</strong>：您可以使用参数化的方式来生成硬件，例如根据输入的宽度或其他参数来生成不同大小的模块：</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">verilogCopy codeparameter WIDTH = 8; // 输入宽度</span><br><span class="line">generate</span><br><span class="line">  // 使用WIDTH参数生成不同大小的硬件</span><br><span class="line">endgenerate</span><br></pre></td></tr></table></figure>

<ul>
<li><strong>层次生成</strong>：您可以在一个<code>generate</code>块中嵌套另一个<code>generate</code>块，以实现更复杂的层次结构。</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line">verilogCopy codegenerate</span><br><span class="line">  // 外层generate块</span><br><span class="line">  generate</span><br><span class="line">    // 内层generate块</span><br><span class="line">  endgenerate</span><br><span class="line">endgenerate</span><br></pre></td></tr></table></figure>



<h3 id="3-Verilog开发工具"><a href="#3-Verilog开发工具" class="headerlink" title="3. Verilog开发工具"></a>3. Verilog开发工具</h3><h4 id="3-1-Verilator"><a href="#3-1-Verilator" class="headerlink" title="3-1 Verilator"></a>3-1 Verilator</h4><p>新手试水：  <a target="_blank" rel="noopener" href="https://blog.csdn.net/Daturasee/article/details/124488821">https://blog.csdn.net/Daturasee/article/details/124488821</a></p>
<p>官方文档： <a target="_blank" rel="noopener" href="https://veripool.org/guide/latest/overview.html">Overview — Verilator 5.012 documentation (veripool.org)</a></p>
<p>进阶文档： <a target="_blank" rel="noopener" href="https://www.itsembedded.com/">https://www.itsembedded.com/</a></p>

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